This invention relates generally to the field of complementary metal oxide semiconductor (CMOS) bias techniques. More particularly, in certain embodiments, this invention relates to a dynamic bias arrangement for CMOS using current steering logic that is particularly applicable to large scale integration.
The trend for a number of years in fabrication of CMOS integrated circuits is toward fabrication of transistors having smaller geometries and thinner gate oxides. These smaller geometries permit faster operation of the circuits and provide for more efficient manufacturing by permitting larger numbers of circuits to be placed on each semiconductor wafer.
Unfortunately, this trend is not without disadvantages. For example, as the geometries of the circuits decrease, the ability of the circuit to withstand large rail-to-rail voltage swings diminishes and the thinner gate oxides of the individual transistor devices exhibit problems with tunneling at a lower voltage. This in turn complicates retention of a standard supply voltage for a particular device or generation of devices. Thus, in order to provide more advanced circuitry operating at higher speeds, more advanced CMOS devices (which are generally operated as rail-to-rail output logic devices) with smaller geometries have required circuitry to adapt to earlier established voltage supplies, or else a new generation of devices operating at lower supply voltages, had to be defined. Thus, in order to advance the state of the art, earlier defined standards on power supply voltage had to be abandoned in favor of newer standards, providing little stability of supply voltage requirements across process generations.
The present invention relates generally to a CMOS logic circuitry. Objects, advantages and features of the invention will become apparent to those skilled in the art upon consideration of the following detailed description of the invention.
In certain embodiments consistent with the present invention, a CMOS circuit arrangement is provided in which relatively thick oxide devices are fabricated along with relatively thin oxide devices on the same chip. High speed logic circuits are fabricated with thin oxide devices as differential logic operating with a low voltage swing. A current source is fabricated using thick oxide devices to drop a large percentage of the supply voltage, protecting the thin oxide devices from damage caused by large voltage swings. An adaptive bias control circuit receives inputs from the logic circuit or elsewhere to control the bias current available from the current source to permit larger currents to pass through the current source at switching times.
A CMOS circuit fabricated using a process that can create thick oxide transistors and thin oxide transistors, consistent with an embodiment of the present invention has a differential logic circuit fabricated of thin oxide transistors, and having a plurality of inputs. A current source supplies bias current to the differential logic circuit, the current source being fabricated using at least one thick oxide transistor.
Another CMOS circuit fabricated using a process that can create thick oxide transistors and thin oxide transistors, consistent with an embodiment of the present invention has a differential logic circuit fabricated of thin oxide transistors, and having a plurality of inputs. A current source, supplies bias current to the differential logic circuit, the current source being fabricated using at least one thick oxide transistor, and the current source having a control input that can determine how much current is available to source to the differential logic circuit. An adaptive bias control provides a control signal at the control input of the current source to selectively control the bias current available to the differential logic circuit.
Another CMOS circuit fabricated using a process that can create thick oxide transistors and thin oxide transistors, consistent with an embodiment of the present invention has a differential logic circuit fabricated of thin oxide transistors, and having a plurality of inputs, the differential logic circuit comprising a pair of matched thin oxide transistors configured as a differential inverter. A current source, supplies bias current to the differential logic circuit, the current source comprising a thick oxide transistor receiving a supply voltage at a drain thereof and coupling a reduced supply voltage to the differential logic circuit through a source thereof, and the current source having a control input at a gate thereof that can determine how much current is available to source to the differential logic circuit. An adaptive bias control provides a control signal at the control input of the current source to selectively control the bias current available to the differential logic circuit.
Many variations, equivalents and permutations of these illustrative exemplary embodiments of the invention will occur to those skilled in the art upon consideration of the description that follows. The particular examples above should not be considered to define the scope of the invention.